A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input “reference” signal. The PLL includes a phase detector (PD), a charge pump, a filter and a voltage-controlled oscillator (VCO), and two dividers in a feedback path. The PD compares falling edges of the clocks at its input and outputs two pulses to the filter, and a filter voltage controls the VCO. In this way, the PLL compares the phase of the input signal with the phase of the signals derived from the VCO, and adjusts the frequency of the VCO to keep the phases matched.
More specifically, the signal from the phase detector is used to control the VCO in a feedback loop. That is, when output pulses of the PD are unaligned, i.e., out of phase, the charge pump activates the VCO to compensate for the phase difference. To do this, the charge pump outputs a current pulse to pull a VCO frequency and/or phase up or down. More specifically, the charge pump outputs a current pulse whose direction, e.g., putting charge into the filter or taking charge out of the filter, depends on which output of the PD is wider. The current pulse flowing in the filter creates a voltage which then controls a VCO frequency.
An output of the VCO is divided to create an output clock as well as the feedback clock. Noise in the output clock is a function of noise in the input clock as well as PLL loop parameters, e.g., charge pump gains, filter values, etc. VCO noise also affects the output noise.
A critical design parameter is the PLL loop bandwidth which controls how much of the input clock noise and the VCO noise make it to the output. If the bandwidth is set high, more of the input noise comes through in the output, whereas at a lower bandwidth the output includes more VCO noise, which is very low at higher frequencies. Accordingly, it is beneficial to operate the PLL at higher bandwidths. However, in current PLL architectures, more input noise would also come through as a result because the input noise is multiplied by divider values. In this way, the effect of increasing the loop bandwidth is amplified by the divider values.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.